Field effect transistor (FET) devices are horizontal devices having a source, a drain spaced apart from the source, and a gate disposed between the source and drain. The source and drain regions are heavily doped semiconductor regions in which the source is doped with the same conductivity type of dopant (either n or p) as the drain. A channel region lies underneath the gate and between the source and the drain. The gate is formed of a gate electrode and a dielectric layer. The dielectric layer is interposed between the gate electrode and the channel region. A voltage imposed on the gate electrode controls the flow of current from the source to the drain within the channel. The performance of the FET is improved by improving the speed with which current carriers make the transition between the source and drain. A bipolar transistor is generally a vertical device having a moderately doped base region interposed between a heavily doped emitter region and a lightly doped collector region. The emitter and collector are doped with one conductivity type of dopant (either n or p) and the base is doped with a second conductivity type of dopant (either p or n respectively). The emitter-base junction is forward biased while the collector-base junction is reverse biased. The forward biased emitter-base junction of an NPN injects electrons (holes for a PNP) into the base region. The base region is sufficiently narrow such that a significant amount of carriers which are injected into the base region reach the collector-base junction. The reverse bias on the collector base junction sweeps electrons (holes) which reach the collector base junction into the collector. The performance of the bipolar device is improved by improving the speed with which carriers travel from the emitter to the collector and decreasing the number of carriers which are lost, through parasitic leakages, during the transition from the emitter to the collector.
FET and Bipolar devices are generally manufactured in silicon. This is because the conductivity of silicon can be easily altered by doping the silicon with a suitable dopant species. Also, silicon is easy to work with because it can be easily oxidized and oxidized silicon is nonreactive with many processing agents. One of the disadvantages of using silicon for semiconductor devices is that the electron mobility is relatively low. A low electron mobility decreases the performance of an FET device because a low electron mobility decreases the speed with which electrons make the transition between the source and the drain. A low electron mobility decreases the performance of a bipolar device because a low electron mobility decreases the speed with which electrons travel across the base region of the device. Also, the slower that electrons travel across the base region, the higher the probability that those electrons will be leaked off the base region by a parasitic component.
In order to increase the carrier mobility of silicon semiconductor devices, layers containing germanium have been incorporated into the structure of the silicon semiconductor device. Germanium has a higher electron and hole mobility than silicon. The prior art has demonstrated that a layer of germanium and silicon can be grown on a silicon substrate so long as the alloy layer is thin enough. The lattice spacing of crystalline germanium is larger than the lattice spacing in crystalline silicon. The difference in lattice spacings produces a lattice strain on the alloy layer. Two dimensional electron and hole gas layers can be formed in such strained alloy layers. These electron and hole gas layers have enhanced electron and hole mobilities when compared to silicon. The FET device structure which takes advantage of the silicon-germanium alloy includes a silicon-germanium alloy layer covered by a silicon layer in the channel region of the FET device. Similarly, the bipolar structure which takes advantage of the silicon-germanium alloy layer includes a silicon-germanium alloy layer in the base region between the emitter and collector of the bipolar device. In both types of semiconductor devices, the inclusion of the silicon-germanium layer increases the performance of the semiconductor device.
The basic problem with the incorporation of the silicon-germanium layer into the semiconductor devices is that many semiconductor devices must be made on the same silicon substrate and they must be isolated from each other. The semiconductor devices must be isolated to prevent parasitic leakages from one device affecting another device. Typical junction and oxide isolation are effective in isolating devices, however, these types of isolation take up too much area and do not allow a sufficient number of devices to be placed in a unit of area on the silicon substrate. Trench isolation is a type of isolation which would be both effective and permit the required device density. The problem with trench isolation is that the trench disrupts the silicon lattice and causes parasitic leakage from the device which the trench isolates. This leakage is more severe in devices incorporating a silicon-germanium layer because the trench cuts through a strained silicon-germanium layer which creates more of a disruption in the semiconductor lattice. Typically, the problem of parasitic leakage associated with trench isolation is cured with various insulating layers grown or deposited on the sidewall of the trench. This approach does not work with a semiconductor device incorporating a silicon-germanium layer because the insulating layers grown or deposited on the surface of the silicon-germanium layer do not address the enhanced sidewall leakage due to the strain in the silicon-germanium lattice structure.